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ARL 25-18

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A PDF document (1.6 MB) attached to Notice of 100% Small Business Set-Aside for Patent Drafting Services, from the Department of the Army. Due Nov 13, 2026, 11:59 AM (UTC-5).

File name: ARL 25-18.pdf

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Invention Disclosure
ARL 25-18

TITLE OF INVENTION:

Pipeline Level Crossing ADC with Error Integral 2nd Stage

EXECUTIVE SUMMARY OVERVIEW:

(the purpose of this overview is to provide a brief summarized overview of the invention as described in this invention disclosure document and a direct explanation on what is new about the invention and information about potential military and commercial uses)

What is this Invention?

(e.g., a short 3-sentence “summarized” description as a more “detailed” description will be required further into this invention disclosure)

Invention Title: Pipeline Level Crossing ADC with Error Integral 2nd Stage The invention solves the low frequency harmonic distortion described in Kurchuck’s dissertation [1] for level crossing analog-to-digital converters. We have simulated a two stage pipeline level crossing ADC using the integral of the error signal to significantly improve the performance of a level crossing analog-to-digital converter. Pipeline level crossing patent pending inventions ARL 21-13, and ARL 24-23 do not use the integrated error signal method for the present invention.
1. What is the basic premise of the design?
Kurchuck [1]

Error signal = Input – LC ADC Output
Bell Curve causes in-band harmonics

Figure 1. Kurchuk’s dissertation shows in-band harmonic distortion for the error signal (Input – ADC Output) for the near zero slope region (“Bell” region) in a sinewave. The bell part of the error signal causes in-band harmonic distortion. High slope regions (sawtooth regions) have harmonic distortion outside the passband. In [1], Kurchuk presents an analysis of harmonic distortion present in level crossing analog-to-digital converters. A new signal capture method is required to overcome the small number of sample points in the bell region to overcome in-band harmonic distortion.

16 Voltage Level, Level Crossing ADC

Error Signal

Voltage (Float), Digital Code

Input Signal

Error Integral

. 005

. 01

. 025
Time(sec)

. 03

. 035

. 04

. 045

Figure 2 shows a simulation of a 16 voltage level, level crossing ADC comparing the integral of the error signal instead to the error signal from Kurchuk [1]. The present invention uses the integral of the error signal (Input – ADC Output). For the integral of the error signal, we see a much faster changing signal. This moves the harmonic distortion for the low slope regions to outside of the passband. The present invention significantly improves the signal capture performance.

Stage 1

Stage 2

Analog Integrator

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