Elegant Additional Materials 9 17 2026
Updated
A PDF document (210 KB) attached to NSF Ecosystem for Low-dimensional Electronics: Growth, Assembly, Nanoelectronics, and Translation (NSF ELEGANT), from the National Science Foundation. Due Dec 18, 2026, 5:00 PM (UTC-5).
File name: Elegant Additional Materials 9 17 2026 Final.pdf
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This document provides additional program design information for ELEGANT proposers. Some of the criteria included here are intended to be illustrative. They may change as a result of the OTASO proposal and negotiation process and/or refinement through the Annual Project Plan (APP) approval process.
ELEGANT Translation Themes
ELEGANT is organized around five Translation Themes. Each Theme is defined by its Translation Endpoint — the industry-adoptable deliverable against which Expert Performer Teams (EPTs) are selected and held accountable. Go/No-Go criteria are Phase-end checkpoints assessing whether each Team has made sufficient progress to justify continued NSF investment; meeting a criterion confirms continued funding, while achieving the Translation Endpoint confirms the Theme has fulfilled its program purpose. Criteria are established at pre-award and may be refined through the Annual Project Plan process, consistent with Section 4.2. Some of the details listed below are illustrative; EPTs are expected to identify the most effective approach to achieving each Theme's endpoint and the overall Translation Endpoint of a full-chip demonstration as defined below at the end of Theme 3.
Theme 1 — Manufacturable Materials Platform
Translation Endpoint: Demonstrate Low-D semiconductor materials using uniform wafer-scale or selective-area synthesis/deposition — that meet industry-defined specifications at both 200 mm and 300 mm wafers, using production-relevant deposition equipment to synthesize the material and production-relevant metrology equipment to characterize it, both on a pathway to manufacturing readiness. Success requires industry partner sign-off confirming specifications are met at both wafer sizes, with both deposition and metrology processes and equipment on a demonstrated production pathway — not synthesis- and metrology-science advances alone. •
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Industry-Defined Low-D Semiconductor Material Quality Specifications. Establish, maintain and refine advanced-node material specifications with two or more industry partners, including requirements for quality, uniformity, defects, and surface/interface properties, applicable at both 200 mm and 300 mm. Initial specifications will be documented in the Annual Project Plan (APP) and refined during Phase 1. Wafer-Scale Material Growth. Scalable Low-D material synthesis meeting the industry-defined quality specifications, via uniform and/or selective-area growth, at both 200 mm and 300 mm, using production-worthy methods including (but not limited to)
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