ELEGANT OTASO 9 17 2026

Technology, Innovation and Partnerships (TIP) Directorate Ecosystem for Low-dimensional Electronics: Growth, Assembly, Nanoelectronics, and Translation (ELEGANT)

OTHER TRANSACTION AGREEMENT SOLUTIONS OFFERING

(OTASO)

Solicitation Number: NSF-OTASO-FY26-ELEGANT
Issue Date: Thursday, September 17, 2026
Proposal Due Date: Friday, December 18, 2026
Program Director: Michael Huff, Ph.D.

1.0 Purpose and Background

1.1 Mission

This solicitation seeks to select (i) an Ecosystem Coordinator and (ii) Expert Performer Teams to constitute and perform activities of the Ecosystem for Low-dimensional Electronics: Growth, Assembly, Nanoelectronics, and Translation (ELEGANT). ELEGANT's mission is to translate Low-D semiconductor technologies from laboratory demonstrations into industrially viable platforms that U.S. microelectronics manufacturers can qualify, fabricate, and deploy. Success in this translation is essential to restoring U.S. leadership in advanced microelectronics and will enable next-generation capabilities in artificial intelligence, high-performance computing, advanced communications and other key technology areas critical to national security and the nation’s overall economic competitiveness.

1.2 Technology Challenge

Moore's Law — the defining principle driving microelectronics innovation for nearly six decades — has become increasingly difficult to sustain as silicon-based transistor scaling approaches its fundamental physical limits. The result is a worsening trade-off — ever-greater investment yielding ever-smaller returns in power, performance, area, and cost, the key microelectronics metrics collectively known as PPAC.
The inability to further reduce silicon channel dimensions below 5 nanometers without severe performance degradation presents an existential challenge to continued integrated circuit advancement that advanced patterning technologies cannot alone overcome. State-of-the-art architectures, including gate-all-around field-effect transistors (GAA-FETs), provide improved electrostatic control. However, the resulting gains in transistor scaling have become incremental and come at a steep price: increasingly complex process integration, tighter manufacturing tolerances, additional patterning and fabrication steps, and rapidly escalating development and production costs.
Complementary FET (CFET) architectures — which vertically stack an n-type and a p-type transistor directly on top of one another — represent the next major scaling step on current